Modifying the PCIe DMA transfer example design for Arria 10 device.

Hi Adzim,

Thank you very much for your reply. I have Emailed you my working directory PCIe_DDR4 which contains all files related to the project.

1) Before, I was doubtful whether the top-level entity DE5A_NET.v is getting updated when the the ep_g3x8_avmm256.v is updated with new design (automatically from modification in Platform Designer System). I got this doubt because the DE5A_NET.v did not change after I modified the .qsys file in the Platform Designer System (In other words,the DE5A_NET.v with just PCIe DMA example design is exactly the same even when I add counter and FIFO IP with the PCIe DMA example design).

But from your reply I assume that even if nothing changed in DE5A_NET.v, the included ep_g3x8_avmm256 module maps the ep_g3x8_avmm256.v and so whatever changes ep_g3x8_avmm256.v have reflected in DE5A_NET.v?

2) If I create an EMIF example design and include the rtl code for counter part, how I can view from my host system that the data is getting written there? Is there any provision in the EMIF example design? Could you elaborate it bit more?

3) Any comment regarding point 2 of my last message..... "When I turn on the simulation option in the Generate HDL GUI (turn on means selecting VHDL/Verilog option. Turned off means selecting none for the simulation option and keeping just ) I gets some error (attached error_simulation.PNG). But when just Synthesis option= Verilog and simulation= none, no error. I am aware that this is something related to counter code which is synthesis-able only. Do you have any suggestion regarding how to make a custom IP out-of counter.v code that is compatible for both synthesis and simulation? "