Modifying the PCIe DMA transfer example design for Arria 10 device.

Hi Adzim,

Sorry for bit delay in responding. I have sent you by email a basic counter Verilog code that I was testing recently. I converted that to a custom IP and added to Platform designer. What I assume is my counter stream data to the Intel Avalon FIFO IP (through the Avalon streaming source interface of counter to the streaming sink of Avalon FIFO IP). Then FIFO IP transfer that data to the DDR4 memory in the DMA transfer example design (Avalon MM slave of FIFO IP to Avalon MM masters of Avalon MM Pipeline Bridge Intel FPGA IP component in the Platform Designer System of the PCIe DMA transfer example).

1) I am curious that since the counter is just streaming data to FIFO (and FIFO does the Avalon MM transfer), do I need to specify any address in my counter code?

2) If we have a Quartus Project File and associated .qsys file is Opened in the Platform Designer. After adding a new custom IP in the Platform Designer system, Validating system integrity and generating HDL, do we want to do any manual modification in the Verilog code (top-level entity) associated with the Quartus Project? I am aware that generating HDL will create a HDL file in the synthesis directory. Should I use that HDL file as my top level HDL of my Quartus Project?

I still have some missing information regarding how my changes in Platform Designer System (.qsys) changes other files in the Quartus Project. It would be perfect if you could point any documentation regarding this.

Is there any reason not to use .qsys file as the top-level entity? When I do that for the DMA transfer example design, I am getting an error "Design requires 1285 use-specified I/O pins -- too many to fit in the 786 user I/O pin locations available in the selected device" . I am attaching the screen shot of this error Capture(4).PNG. Any feedback regarding this issue?

I have noticed keeping .sdc or verilog file as top-level entity did not throw this error.