Forum Discussion
Honored ContributorModifying ddr controller parameters
I have designed a new pcb with a cyclone iii and a ddr memory. I have not respected the track lengths. Anyone knows how to modify ddr controller parameters in order to fit a more relaxable design? (not for the best performance) When I run the mem_test it says:
Testing RAM from 0x2000000 to 0x3ffffff -Data bus test passed -Address bus test passed -Byte and half-word access test passed -Testing each bit in memory device . . . failed at address 0x2003C1C Presss enter to continue or 'q' to quit. And the problem is repeated in other memory regions. The ddr controller cannot read more than 15388 bytes. Many thanks. ifdm4 Replies
Altera_ForumI upload some captures measured with the oscilloscope in the new pcb. Also I have captured the same signals in the altera development kit. The pictures from the left correspond to a2 in the pcb and a2 in the kit; the two pictures from the right correspong to a0 in the pcb and a0 in the kit.Any idea wich phenomenon is taking place? Many thanks.
ifdm P.D They have been taken while running mem_test app.- Altera_Forum
I have found how to modify the drive strength (drive strength reduced) in the ddr controller and now the program checks 131072 bytes, but the test continues failing. About the dynamic termination scheme I have read that it's impossible to apply with a ddr memory (but it's possible for ddr2 and ddr3). In this line, any idea of how can I continue improbing the signal integrity?
- Altera_Forum
How can I modify the drive strength and apply a dynamic termination scheme?
Many thanks, ifdm - Altera_Forum
Reducing the memory frequency is the most promising method to make the design work though, if length mismatch or e.g. crosstalk is causing the failure. Modifying drive strengths and/or dynamic termination schemes may also improve the situation.
