modelsim simulation error

hi,

i am trying to simulate my custom ip in model sim.

i have developed the ip only for writing data to it from NIOS II processor.(fig1) in verilog.

my qsys file is as shown in fig 2

i have mentioned a 2 bit slave adress, so i expectd data to be written as

when slave adress is 00 slave write data is aaaaaaaa

when slave adress is 01 slave write data is bbbbbbbb

when slave adress is 10 slave write data is ccccccccc

when slave adress is 11 slave write data is dddddddd

when i tried to pass four 32 bits data sequentially,, i am getting the response like this.(fig 4)

it seems to be fine till third slave adress, thereafter instead of slave adress 11, 01 is coming as seen in figure.

can anybody help me to correct this?