Forum Discussion
Modelsim error
Hii i am using Modelsim student edition for the simulation of my edge detection code.
I am getting the following error.... ** Error: fixed_pkg Unbounded number passed, was a literal used?** can any one please suggest what is the meaning of this error??? Thanx and regards!!13 Replies
- Altera_Forum
Honored Contributor
Run time error is an error that occurs during runtime - ie. during simulation. I do not get a problem compiling your code, but I cannot run your code as I do not have the testbench you are using to simulate it.
- Altera_Forum
Honored Contributor
--- Quote Start --- Without your testbench - there is not much I can do as it compiles just fine. I assume your error is runtime? Debugging is really something you should be doing. --- Quote End --- I am trying to debug it from one week.Can you give me outline how to debug a code.And what is this run time error.I am using an small image of size 64 *64.How to deal with run time error. - Altera_Forum
Honored Contributor
Without your testbench - there is not much I can do as it compiles just fine. I assume your error is runtime?
Debugging is really something you should be doing. - Altera_Forum
Honored Contributor
--- Quote Start --- As I have said before, you have dx and dy declared as sfixed, but then casting to a unsigned - why? --- Quote End --- Thank you for replying.. Sorry now I get it. Even if i will change it to sfixed it will be same as I am taking abs value of it. So no need to convert it in unsigned. I did the changes but the error is same as above.Can you suggest any thing.I am attaching updated file with it. - Altera_Forum
Honored Contributor
As I have said before, you have dx and dy declared as sfixed, but then casting to a unsigned - why?
- Altera_Forum
Honored Contributor
Thank you so much for your reply.I tried the line suggested by you .It is showing the following error.
no feasible entries for subprogram "to_unsigned".So I changed the mod _d to (9 downto 0).
mod_d <= unsigned(to_ufixed(resize((abs(dx)+abs(dy)),9,0)));
This is giving correct mod and division values with respect to different dx and dy values. Now the error is same.if I am changinf the simulation setting to (Simulation-Run time option-message severity-error),it is showing following error. # ** error: fixed_pkg unbounded number passed, was a literal used? # time: 783 us iteration: 0 process: /camera/uut/angle1 file: c:/users/embedded/desktop/new/fixed_pkg.vhdl # break in subprogram mine at c:/users/embedded/desktop/new/fixed_pkg.vhdl line 2061.
So is it mean thet error is in process angle1.As i read in some sites that this error caused if we use negative indexing,which I have not used through out the code.Please help me with this .I am not getting what to do.I am attaching the new file with some modifications in it.
- Altera_Forum
Honored Contributor
dx and dy are declared as sfixed(), but you're trying to convert it to ufixed. There is no to_ufixed function from sfixed because such a thing would not make much sense. If you really insist on using ufixed, you need to type cast it yourself via:
mod_d <= to_unsigned(ufixed(resize((abs(dx)+abs(dy)),7,0))); --Resize the result to 8 bits But given dx and dy are signed - im guessing things are going to start to go wrong.. - Altera_Forum
Honored Contributor
--- Quote Start --- Please find attachments ,this is the main code file.If you need any other file then please tell me. --- Quote End --- This is the same code with some correction in it.please help me with it. - Altera_Forum
Honored Contributor
--- Quote Start --- Without all of the signal descriptions, we wont be able to give a full answer. Please attach the full code to your post (dont paste it). --- Quote End --- Please find attachments ,this is the main code file.If you need any other file then please tell me. - Altera_Forum
Honored Contributor
Without all of the signal descriptions, we wont be able to give a full answer.
Please attach the full code to your post (dont paste it).