modelsim error when simulate : cannot load \eda\mentor\modelsim\convert_hex2ver.dll

Here is the problem module...

`timescale 1ns/1ns
module VGA_1
(
    CLOCK_50, KEY,
    VGA_CLK, VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS, VGA_BLANK_N, VGA_SYNC_N
);
input CLOCK_50;
input  KEY;
wire CLOCK_50;
wire  KEY;
output VGA_CLK;
output  VGA_R, VGA_B, VGA_G;
output VGA_HS, VGA_VS, VGA_BLANK_N, VGA_SYNC_N;
wire VGA_CLK;
reg  VGA_R = 8'd0;
reg  VGA_B = 8'd0;
reg  VGA_G = 8'd0;
reg VGA_HS = 1'b1;
reg VGA_VS = 1'b1;
wire VGA_BLANK_N;
reg VGA_SYNC_N = 1'b1;
wire rst;
assign rst = ~KEY;
// 25 MHz clock generation
reg clk_25M_cnt = 1'b0;
reg clk_25M = 1'b0;
assign VGA_CLK = clk_25M;
always @ (posedge CLOCK_50 or posedge rst)
begin
    if(rst)
    begin
        clk_25M_cnt <= 1'b0;
        clk_25M <= 1'b0;
    end
    else
    begin
        
        if(clk_25M_cnt)
        begin
            clk_25M_cnt <= 1'b0;
            clk_25M <= ~clk_25M;
        end
        else
        begin
            clk_25M_cnt <= 1'b1;
        end
        
    end
end
// Color output generation
reg  vga_state = 2'd0;
always @ (posedge CLOCK_50 or posedge rst)
begin
    if(rst)
    begin
        VGA_R <= 8'd1;
        VGA_G <= 8'd0;
        VGA_B <= 8'd0;
    end
    else
    begin
        
        if((VGA_R == 8'd0) || (VGA_R == 8'd255))
        begin
            VGA_R <= 8'd0;
            if((VGA_G == 8'd0) || (VGA_G == 8'd255))
            begin
                VGA_G <= 8'd0;
                if((VGA_B == 8'd0) || (VGA_B == 8'd255))
                begin
                    VGA_B <= 8'd0;
                    VGA_R <= VGA_R + 8'd1;
                end
                else
                begin
                    VGA_B <= VGA_B + 8'd1;
                end
            end
            else
            begin
                VGA_G <= VGA_G + 8'd1;
            end
        end
        else
        begin
            VGA_R <= VGA_R + 8'd1;
        end
        
        case (vga_state)
            2'd0:begin
                vga_state <= vga_state + 2'd1;
            end
            2'd1:begin
                vga_state <= vga_state + 2'd1;
            end
            2'd2:begin
                vga_state <= vga_state + 2'd1;
            end
            2'd3:begin
                vga_state <= vga_state + 2'd1;
            end
            default:begin
                vga_state <= 2'd0;
            end
        endcase
        
    end
end
// Blanking signal generation
assign VGA_BLANK_N = (vga_blanking_h && vga_blanking_v);
// Sync signal generation for horizontal
reg  vga_disp_cnt_h = 0;
reg vga_blanking_h;
// Horizontal counter
always @ (posedge CLOCK_50 or posedge rst)
begin
    if(rst)
    begin
        vga_disp_cnt_h <= 0;
    end
    else
    begin
        if(vga_disp_cnt_h == 1600)            // 800 pixels
        begin
            vga_disp_cnt_h <= 0;
        end
        else
        begin
            vga_disp_cnt_h <= vga_disp_cnt_h + 12'd1;
        end
    end
end
// Horizontal sync
always @ (posedge CLOCK_50 or posedge rst)
begin
    if(rst)
    begin
        VGA_HS <= 1'b1;
        vga_blanking_h <= 1'b1;
        VGA_SYNC_N <= 1'b1;
    end
    else
    begin
        // Front porch (16 pixels)
        if(vga_disp_cnt_h >= 1568)    // 784 pixels
        begin
            VGA_HS <= 1'b1;
            vga_blanking_h <= 1'b0;
            VGA_SYNC_N <= 1'b1;
        end
        // Horizontal sync (96 pixels)
        else if(vga_disp_cnt_h >= 1376)    // 688 pixels
        begin
            VGA_HS <= 1'b0;
            vga_blanking_h <= 1'b0;
            VGA_SYNC_N <= 1'b1;
        end
        // Back porch (48 pixels)
        else if(vga_disp_cnt_h >= 1280)    // 640 pixels
        begin
            VGA_HS <= 1'b1;
            vga_blanking_h <= 1'b0;
            VGA_SYNC_N <= 1'b1;
        end
        // Pixel dipsplay time (640 pixels)
        else if(vga_disp_cnt_h >= 0)        //   0 pixels
        begin
            VGA_HS <= 1'b1;
            vga_blanking_h <= 1'b1;
            VGA_SYNC_N <= 1'b1;
        end
    end
end
// Sync signal generation for vertical
reg  vga_disp_cnt_v = 0;
reg vga_blanking_v;
// Vertical counter
always @ (posedge CLOCK_50 or posedge rst)
begin
    if(rst)
    begin
        vga_disp_cnt_v <= 0;
    end
    else
    begin
        if(vga_disp_cnt_v == 525)            // 525 lines
        begin
            vga_disp_cnt_v <= 0;
        end
        else
        begin
            if(vga_disp_cnt_h == 1376)
            begin
                vga_disp_cnt_v <= vga_disp_cnt_v + 11'd1;
            end
        end
    end
end
// Vertical sync
always @ (posedge CLOCK_50 or posedge rst)
begin
    if(rst)
    begin
        VGA_VS <= 1'b1;
        vga_blanking_v <= 1'b1;
    end
    else
    begin
        // Front porch (10 lines)
        if(vga_blanking_v >= 515)            // 515 lines
        begin
            VGA_VS <= 1'b1;
            vga_blanking_v <= 1'b0;
        end
        // Vertical sync (2 lines)
        else if(vga_blanking_v >= 513)    // 513 lines
        begin
            VGA_VS <= 1'b0;
            vga_blanking_v <= 1'b0;
        end
        // Back porch (33 lines)
        else if(vga_blanking_v >= 480)    // 480 lines
        begin
            VGA_VS <= 1'b1;
            vga_blanking_v <= 1'b0;
        end
        // Line dipsplay time (480 lines)
        else if(vga_blanking_v >= 0)        //   0 lines
        begin
            VGA_VS <= 1'b1;
            vga_blanking_v <= 1'b1;
        end
    end
end
endmodule

And the test bench for modelsim...

`timescale 1ns/1ns
module VGA_1_TB
(
);
reg clk = 1'b0;
reg  KEY = 1'b0;
wire VGA_CLK;
wire  VGA_R;
wire  VGA_B;
wire  VGA_G;
wire VGA_HS;
wire VGA_VS;
wire VGA_BLANK_N;
wire VGA_SYNC_N;
VGA_1 u (clk, key, VGA_CLK, VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS, VGA_BLANK_N, VGA_SYNC_N);
initial
begin
 # 0  clk = 1'b0;
end
always
begin
 # 5  clk = ~clk;
end  
endmodule

Basically, get the error I mentioned whenever I try to simulate.

And now, when I try to simulate another project that used to be working, I get an error too.

All went to **** overnight. It worked one evening and didn't the next morning... without any changes to my computer, OS, etc.

Any help is greatly appreciated !