Yes, you can perform timing simulation with .vho (netlist de simulation timing) with .sdo (standard delay ) files generated by quartus. See Quartus->Assignment->EDA tool settings -> simulation -> tool name, choos Modelsim Altera.
And then, Quartus -> Processing -> start -> start EDA netlist writer.
but, this type of simulation will take 100x of functional simulation time In Modelsim, you can associate .sdo :
File -> add to project -> add simulation configuration ->
in SDF tab, click add... add your .sdo file (located in project_dir\simulation\modelsim)
in design tab, change resolution to ps (picosecond).