Honored Contributorcan we perform a timing simulation for our design using the modelsim altera web edition? if yes can anybody plz suggest me a good tutorial page for the same? [i absolutely loved the 4 hours quartus web training module.. but alas... it gave very little info on using modelsim]
Honored ContributorYes, you can perform timing simulation with .vho (netlist de simulation timing) with .sdo (standard delay ) files generated by quartus. See Quartus->Assignment->EDA tool settings -> simulation -> tool name, choos Modelsim Altera.
And then, Quartus -> Processing -> start -> start EDA netlist writer. but, this type of simulation will take 100x of functional simulation time In Modelsim, you can associate .sdo : File -> add to project -> add simulation configuration -> in SDF tab, click add... add your .sdo file (located in project_dir\simulation\modelsim) in design tab, change resolution to ps (picosecond).Honored Contributor1. Create your waveform vector file in Quartus II
2. Export this file to vhdl test bench (file->export) 3. Click, asssigments->settings->EDA tool settings->Simulation , choose modelsim altera. chooose compile test bench in native link settings panel, click test benches, click new, chosse any name for test bench, in test bench entity write: <your_top_level_entity>_vec_tst in instance name write : i1 chosee the file generated in step 1 in test bench files. 3. Compile your project. 4. click, tools->eda simulation tools: run eda rtl simulation for functional simulation or run eda gate level simulation for timing simulation. After this steps quartus ii opens modelsim an starts the simulation.
