Honored Contributor
Honored ContributorSynchronous generally means a clock, but it can also be thought of as a repeated relationship. So in your case, put a generated clock on RD, where the -source is whatever clock feeds it. To say that the same edge sending the data is capturing it based on RD, do a "set_multicycle_path -setup 0 -to [get_clocks RD_CLK]" where RD_CLK is the name of the generated clock you applied to RD.
You basically said the same edge sending your edge is latching it, i.e. it's a 0ns setup relationship. So if your DATA delay is 1ps before the RD output, you'll make timing. So do a "set_outptu_delay -clock RD_CLK -max 2.0 [get_ports DATA*]" and you've made an external data delay of 2ns, so now DATA has to leave 2ns before RD_CLK. Of course, that all assumes the same clock drives data off RD as drives DATA. Your other option, which is probably better, is to have another output of the PLL drive RD, and phase-shift it by ~2.5ns, i.e. enough that if the delays are all matched it will meet timing. In this case, your default setup relationship is 2.5ns, so you don't need the multicycle. The set_output_delay requirement is the same though. Hope that helps.
