Forum Discussion
New ContributorMixed I/O pin standards and VCCIO
Hello,
Yes there is. You can use Chip/Pin Planner under Assignment tab on your Quartus.
This is the tutorial video that you can refer to: https://www.youtube.com/watch?v=Bt-yDRReKZw
We have a few tutorial videos that you can refer to on our Youtube channel: Intel FPGA
Hope this helps.
Amin.
Regular ContributorHello,
You can only use 1.2 V Vccio for input and output of 1.2 V LVCMOS.
The Intel Cyclone 10 GX devices support OCT in all FPGA I/O banks. For the 3 V I/Os,
the I/Os support only OCT without calibration. OCT with calibration is available for LVDS I/O and so as Differential SSTL-12.
You may look for further details on your device GPIO document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
Thank you,
Amin
New ContributorThank Amin for your reply.
Can you clarify the following general rule? Per "Intel Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook" (C10GX51003 | 2020.09.25) Page 91, Table 34,
1) for a 1.2 V LVCMOS output pin, must VCCIO be 1.2 V?
2) for a differential SSTL-12 output pin, must VCCIO be 1.2 V?
3) for an LVDS output pin, , must VCCIO be 1.8 V?
- AminT_Intel
Hello,
1) for a 1.2 V LVCMOS output pin, must VCCIO be 1.2 V?
Yes.
2) for a differential SSTL-12 output pin, must VCCIO be 1.2 V?
Yes for the Vccio output pin.
3) for an LVDS output pin, , must VCCIO be 1.8 V?
LVDS I/O bank supports differential and single-ended I/O standards up to 1.8 V.
Thank you.
- Twincreeks
Thank you for your further clarification. Your answer to my third question is still ambiguous. LVDS has two meanings in the handbook, the general LVDS /IO bank (comparing with the 3 V I/O bank) and the specific LVDS I/O standard (comparing with SSTL-12). What I am asking is the specific LVDS I/O standard, while your answer is about the I/O bank. For an output pin in the LVDS I/O standard, must VCCIO be 1.8 V?
- AminT_Intel
Hello,
Yes you need Vccio 1.8 V output for. LVDS I/O Standard.
Thank you.
