minimum time for IO pin to damage

The Altera provided informations says a bit more.

For the negative input voltage, the clamp characteristic is specified in the IBIS files. In this operation, the interesting question is, if you can achieve some current limitation, e.g. by a resistor between the ESD protection device and the input. Otherwise, negative input currents will be absorbed completely by the FPGA rather than the protection device. An asymmetric voltage limiter would be more reasonable, of course.

For the positive direction, Altera has started with Cyclone III to specify tolerable relative duration of input overshoots. Although it doesn't directly answer your question, it clarifies, that they are considering voltages above 4.1 V. Cyclone III should be expected more sensitive to overvoltages than Cyclone, because it's a smaller structured IC technology.