Minimum pulse width violation

Thanks for your help JK,

Here is the full error below:

 
-0.127 2.000 2.127 High Pulse Width fclk Rise circular_buffer:xncb|input_buffer:ib|altsyncram:altsyncram_component|altsyncram_g9r1:auto_generated|q_b
 

Some of the signals that drive the input of memory are inferred as latches by the compiler. Here is the code that drives the memory shown below:

 
always @(pstate)
begin
case(pstate) 
s0:
begin //state 0 resets all control signals and aligns the read pointer of the 
acc_reset<=0; //circular input buffer to the latest input sample. If the wrptr for the
rdptrw<=0; //input buffer isn't zero, then decrement the wrptr by one and set that 
calc<=0; //equal to the read pointer. This is because everytime a new value is written
wn_w<=0; //to the input buffer via xn_w, then the write pointer automatically increments
if(wrptr !=0) //to the next location. Thus, one minus the current wrptr gives the location of
rdptr<=wrptr-1; // the most recent input sample.
else
rdptr<=(L-1);
end
s1:
begin
counter<=0; //reset the counter to zero since this is the first product of the convolution.
end //also delay by one cycle to accomodate memory latency
s2:
begin
rden<=1; //assert read enable to read first coefficient from memory. Also clear the accumulator.
acc_reset<=0;
end
s3:
begin
rden<=0; //now that the old coefficient is output, assert calc to calculate a new coefficient
calc<=1; 
wn_w<=0;
end
s4:
begin
rden<=0; //increment the counter for the next multiplication
calc<=0;
wn_w<=0;
counter<=counter+11'd1;
end
s5:
begin
wn_w<=1; //store the new coefficient
end
s6:
begin
wn_w<=0; //output input value to begin multiplication
rden<=1;
end
s7:
begin
rden<=0; //perform multiplication and latch it in the MAC
mac_latch<=1;
if(rdptr==0) //if the current input sample is coming from the bottom
begin //of the input buffer, then wrap around to the top in a circular
rdptr<=(L-1); //fashion. Otherwise, just decrement the pointer.
end
else
begin
rdptr<=rdptr-1;
end
rden<=0;
if(!(counter==(L))) //if there are still more convolution multiplications left
begin //increment the read pointer to the coefficient buffer
if(rdptrw==(L-1))
rdptrw<=0;
else
rdptrw<=rdptrw+1;
end
end
s8:
begin
mac_latch<=0; //calculate the next coefficient
rden<=1;
end
s9:
begin
calc<=1; 
wn_w<=0;
rden<=0;
end
s10:
begin
calc<=0;
end
s11:
begin //if there are no more convolution products to be calculated,
firdone<=1; //then convolution is finished. Assert firdone to indicate this condition.
acc_reset<=1; //also reset the accumulator for the next cycle.
end
s12:
begin
//wn_w<=0;
firdone<=0; //deassert firdone
end
default:
begin
rden<=0;
calc<=0;
firdone<=0;
acc_reset<=0;
wn_w<=0;
rdptr<=0;
rdptrw<=0;
counter<=0;
end
endcase
end

It is the output part of a state machine that operates a circular buffer. For some reason, I recieved these warnings that stated that some of the signals input into the memory were inferred as latches:

 
Warning (10240): Verilog HDL Always Construct warning at circular_buffer.v(196): inferring latch(es) for variable "rden", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at circular_buffer.v(196): inferring latch(es) for variable "calc", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at circular_buffer.v(196): inferring latch(es) for variable "firdone", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at circular_buffer.v(196): inferring latch(es) for variable "acc_reset", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at circular_buffer.v(196): inferring latch(es) for variable "wn_w", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at circular_buffer.v(196): inferring latch(es) for variable "rdptr", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at circular_buffer.v(196): inferring latch(es) for variable "rdptrw", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at circular_buffer.v(196): inferring latch(es) for variable "counter", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at circular_buffer.v(196): inferring latch(es) for variable "mac_latch", which holds its previous value in one or more paths through the always construct

Any help would be greatly appreciated.