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Thanks for the help ashishkaps. If the clock frequency is acceptable, then what could be causing this problem?
I can't avoid the latches. The altsyncram memory is synchronous. Every input to the module is latched with the clock. It seems that the error is occuring with that component.
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There may be a terminology problem here, a 'latch' is something that looks like this
LATCH_PROC : process(clk, d)
begin
if clk = '1' then -- Note: Simply comparing clk to '1', not an edge
q <= d;
end if;
end process;
A flip flop looks like this
FLOP_PROC : process(clk, d)
begin
if clk = '1' and clk'event then -- Note: Looking for a rising edge on clk
q <= d;
end if;
end process;
Latches are almost always avoidable, and in an FPGA they must be avoided to get a working design. Edge triggered flip flops are required.
Odds are that the syncram is not the source of the problem, it is just the signal that is reporting the error.
- How are your inputs to the memory generated? (i.e. Latch_Proc or Flop_Proc)
- Is the clock free running from either a clock input pin or the output of a PLL? Or is it generated internally in the design?
Kevin Jennings
Honored Contributor
