Minimum pulse width violation

Not at all i dont think 120 Mhz can cause any problem...i have worked with 225 Mhz and i never got dis violation.

I dont have much idea of the cause but i dont think inferring a latch is a good idea and as you mentioned latch with a clock then it is shud be removed as far as i know.

Slow and fast models are corners of a model. The results of a slow model helps you determine hold violation. You can ignore setup violations if they are of very small -ve slack but if the -ve slack for setup violations are big then they shud be considered. But no hold violation is acceptable in slow corner.

In fast corner its just the reverse.

The results of a fast model helps you determine setup violation. You can ignore hold violations if they are of very small -ve slack but if the -ve slack for hold violations are big then they shud be considered. But no setup violation is acceptable in fast corner.

One thing to be noted is that even if your fast as slow corners show good results with reference to my above statements you have to take in account that what the +ve slack is in these corners. If it is very small say 0.4 ns then you need to work on optimizing your design as your design wont be exposed to fast or slow corner speed grades when in application. It will be working in some industrial speed grade which is the correct balance of the two.

you can say suppose you are having a setup violation in fast corner then you design can never meet any setup requirements with the current optimization you have applied or if you are having hold violations in slow corner then your design can never meet hold timings with current settings.

I hope you understand what i mean to say.

Fast and slow corners are the limits to check violations in the best cases and if the respective setup or hold violation fails then you have to turn up with some good quartus settings for your designs to meet these timings or in worst case change the rtl code.