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Honored Contributor
Honored ContributorMinimum IO clock input
My design requires a clock input of 1MHz that can be locked with a pll. Currently i have a cyclone II fpga but in the pll megafunction i cant input a frequncy of anything lower than 50MHz or divide e...
Altera_ForumHonored Contributor
Honored Contributorthe minimum PLL input frequency for CII should be 10 MHz, see page 66:
http://www.altera.com/literature/hb/cyc2/cyc2_cii51005.pdf
