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Honored Contributor
Honored ContributorMinimal pulse duration for VIC to recognize an interrupt?
Hi I'm using a cyclone III (EP3C40F48I8N) with a Nios II/f . On a custom component I have a tristate slave interface with an "Interrupt Sender". I found out, that a pulse on the irq of 1...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- ...the interrupt service routine reads the interrupt status register, stores its value somewhere, clears it and then returns... --- Quote End --- Yes, that's what I would normally do with an edge-triggered PIO interrupt source, but in this case I can't clear the interrupt status register, because this would mean (if I'm not mistaken) I had to clear the logical signal on the interrupt pin too, which is impossible as this pin only goes low after all pending data has been read from the LAN9211. But - writing this answer - I just had an idea: What about disabling the interrupt source inside the isr. In this case the LAN9211 can drive the irq pin high for as long as it wants, without the Nios reacting on it. And when I actually have time to read the data I can re-enable the interrupt source. Does this sound reasonable, or will I get other problems by disabling and re-enabling interrupt sources inside an isr?
