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You should keep your IRQ asserted until it is cleared by the software ISR routine. I'm not sure the VIC's behaviour is defined or guaranteed if you clear the IRQ yourself before that.
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Yes, normally I would agree on this. In my case the periferal is an ethernet controller (LAN9211), programmed to send an interrupt as soon as new data is available. The controller asserts the irq high until the data is read by the Nios. If I don't want to read the data inside the interrupt routine (because of runtime determinism), I can't reset the irq and because the "Interrupt Sender" component is level sensitive, the isr will be called non stop.
So what I did was implementing a vhdl edge-detector on the irq input that generates a pulse of 1 clock cycle which, as stated above, is not long enough to be caught by the VIC.
Therefore I'm trying to figure out how long I would have to stretch the pulse to be caught.
Honored Contributor
