Forum Discussion
8 Replies
- Altera_Forum
Honored Contributor
You might have to re-generate some IP cores such as PLLs and Nios II etc.
- Altera_Forum
Honored Contributor
Yes the migration issues really depend on the IP you are using.
If you are using SOPC builder and NIOS the difficulty is higher than if you are just using memories and PLL's but you may need to regenerate code IP blocks in either case. I have taken a design from Quartus 6 to 13.1 through the various versions in between. The primary issue I had was with the FFT core changing it's IO interface at one point, but most designs will compile with little issues. Pete - Altera_Forum
Honored Contributor
Triple Speed Ethernet (if you use it) core needs to be manually replaced to newer one in 13.1.
- Altera_Forum
Honored Contributor
You can try to open your 9.1 QAR with 13.1 to see if there is any auto-upgrade performed or any warning prompting on core need to be regen. Then regen the specific cores.
- Altera_Forum
Honored Contributor
Thank you all for your replies !
- Altera_Forum
Honored Contributor
you are welcome.
- Altera_Forum
Honored Contributor
this is something from SOPC to never QSYS based design. I not sure what is your design, i guess if not consists of many complicated components, you may just rebuild directly with v13.1 .
- Altera_Forum
Honored Contributor
There were quite a few issues with QSYS, PCIe, and Transceiver cores, but at the end everything was resolved.