Forum Discussion
Altera_Forum
Honored Contributor
10 years agoSo i am think better looks to screenshots.
Basicly i am use for debug 5CGTFD9 F35 this is standart chip for Cyclone V dev kit. And for understand full line my question looks to this: step 1. Ref design project scat/gat dma for pcie gen2. (warning! - in this case - "zero changes" only compile ref design) P/N FPGA for design 5CGTFD9 F35 compile / program / try - its work! step 2 We are ready to prototype and use cheap C5GTD5 only in package F23 (484 pins fbga). And i am simply in my quartus change device to C5GTD5С5F23, say YES about remove pin assign from project. Comple - succefull ! Great - look to result. Fitter location for one pin have error. looked please. normally in pinout its C8 ! About inverted diff pairs i am double check.