Microcontroller for ADC 0831 in VHDL

Hello,

I am attempting to write a micro controller program in VHDL for my Altera Max cPLD to work with the ADC 0831. I've read the instructions on the data sheet several times and I think it goes something like this:

- Chip Select holds '0'

- Data line goes to '1',

- Each NGT of the clock to the ADC the data will appear MSB first

I don't know.. I'm confused and a noob. Can someone please offer advice?

 ENTITY adc IS
PORT(clk_in: IN BIT;
     clk_out, cs: OUT BIT;
     data: INOUT BIT;
     temperature: OUT BIT_VECTOR (7 DOWNTO 0));
END adc;
ARCHITECTURE one OF adc IS
BEGIN
    PROCESS (clk_in)
        VARIABLE count: INTEGER RANGE 0 to 21;
    BEGIN
        IF clk_in = '1' AND clk_in'EVENT THEN
            count := count + 1;
            
            CASE count IS
            
            when 1 => cs <= '1'; clk_out <= '0';
            when 2 => cs <= '0'; clk_out <= '1'; 
            
            when 3 => clk_out <= '0';  
            when 4 => clk_out <= '1';  
            
            when 5 => clk_out <= '0'; temperature(7) <= data; 
            when 6 => clk_out <= '1'; temperature(7) <= data; 
            
            when 7 => clk_out <= '0'; temperature(6) <= data; 
            when 8 => clk_out <= '1'; temperature(6) <= data;
            
            when 9 => clk_out <= '0'; temperature(5) <= data; 
            when 10 => clk_out <= '1'; temperature(5) <= data;
            
            when 11 => clk_out <= '0'; temperature(4) <= data; 
            when 12 => clk_out <= '1'; temperature(4) <= data;
            
            when 13 => clk_out <= '0'; temperature(3) <= data; 
            when 14 => clk_out <= '1'; temperature(3) <= data;
            
            when 15 => clk_out <= '0'; temperature(2) <= data; 
            when 16 => clk_out <= '1'; temperature(2) <= data;
            
            when 17 => clk_out <= '0'; temperature(1) <= data; 
            when 18 => clk_out <= '1'; temperature(1) <= data;
            
            when 19 => clk_out <= '0'; temperature(0) <= data; 
            when 20 => clk_out <= '1'; temperature(0) <= data;
            
            when OTHERS => cs <= '1';
            
            END CASE;
        END IF;
    END PROCESS;
END one;  

The clock to the cPLD is 32.768 kHz which means the clock to the ADC is half that, where the minimum frequency to the ADC is 10kHz so that should be fine.

Cheers