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Altera_Forum
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16 years ago

Metastability issue? How to clock in high speed ASYNCH Data

Dear Gurus, I am relatively new to VHDL and hardware so here goes… I have designed a board that receives asynchronous data from a PC via USB @ ~ 12mb/s via an FTDI device (FT2232H). The ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Hi,

The speed of fifo will be limited due to timing rules of any device(setup/hold). 1ns is pretty high speed(1Gig) and not achievable in fpgas yet. You may hit 300MHz in best devices(stratix iv).

RdEmpty signal update is delayed due to internal pipeline(synch pipeline defaults to 2 in megawizard, I believe).