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Altera_Forum
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16 years ago

Metastability issue? How to clock in high speed ASYNCH Data

Dear Gurus, I am relatively new to VHDL and hardware so here goes… I have designed a board that receives asynchronous data from a PC via USB @ ~ 12mb/s via an FTDI device (FT2232H). The ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Hi Folks,

Thank you for taking to the time respond (and for going easy me).

I’ll stick with the DCFIFO and make sure the USB chunks are small enough to fit safely.

Rbugalho is right – I am confused as I’m fairly new to this. Just as quick test I had a 1s clock connected to rdreq, redclk (and an LED) to clock the data back onto the USB input put so I could read it back. I got confused as to why it was taking ~5 clks for the rdempty signal to disappear after I had written to it. I have now attached the 50MHz clk to the rdclk and assert the rdreq to get data out.

Just out of interest, do anyone know if there are any timing constraints on the width of the wrclk – for example could this be as little as 1ns?

Thanks again or your help and advice, and for such a rapid response.

Best regards,

H