Metastability issue? How to clock in high speed ASYNCH Data

You are on the right track. dc fifo contains the neccessary clock domain transfer circuitry. They are reliable.

All what is left is control the buffering i.e. data transfer without getting your fifo empty or full.

reading empty fifo or writing to full fifo is not advised...

buffering control can be done by letting the fifo have a suitable depth and suitable start level then it simply provides the required so called elasticity of rate differences. The depth is dependant on your input burstiness.

In short: I will let my fifo first write to a predetermined depth level then start read/write cycles and keep a wacth on empty/full flags.