Metastability issue? How to clock in high speed ASYNCH Data

FYI, I'm not familiar with the FTDI chips.

But if you have a 60 MHz clock on one write side and a 50 MHz clock on the read side, using a dual clock FIFO is, IMHO, the best aproach.

Otherwise, you can't keep up with the write bursts from the USB chipç.

Assuming those two clocks are not related, you should generate the FIFO with 2 or more synchronization stages.

Regarding the read process, you sound a bit confused, but it's the same as for a single clock FIFO and depends on weather you've generated a "legacy" or "read-ahead" FIFO.

Depending on how you've configured your FIFO, asserting rdreq when rdempty is active can cause the FIFO to become corrupted so you need to be carefull about that.