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Altera_Forum
Honored Contributor
16 years agowell I am using both methods and both failed. I just made a custom program to check where the failure is located. Anyway, the data width as I mentioned is 64 bit and the burst length is 4 for the SDRAM controller, I just took the STANDARD design and modified the data bus width to 64. I am using a read master by a SG-DMA (with 3 bit burstcount signal width), and a write master by the Nios II processor data master.