memory controller

Have you read through Altera's memory controller user guides? They might give you an idea of how they are architected:

http://www.altera.com/technology/memory/mem-index.jsp

Also, there are the OpenCores controllers:

http://www.opencores.org/project,ddr_sdr

http://www.opencores.org/project,hpdmc

http://www.opencores.org/project,hssdrc

http://www.opencores.org/project,sdram_controller

Basically the controller is broken into two major parts; the control path, and the datapath. The two parts have their own caveats for different reasons.

The datapath can be difficult because of timing. The capturing of read data is the trickiest part. FPGAs have dedicated circuitry to assist with this.

The control path becomes difficult when you want to start maximizing the controller's efficiency and implementing advanced algorithms (bank interleaving, only refreshing parts of the memory that need it, etc.). You can spend years tweaking and enhancing the controller to get this just right.

Jake