Megawizard FIFO problem: Write and read request filling FIFO!

So I knew about gray counters about as much as everyone else, they follow a count sequence that only flips one bit at a time. So I made an asynch FIFO and created a simple simulation where I could see the gray code counters increment. Looking in the RTL view, there is a parity register, a count register and decode/encode logic to calculate the next state. The parity register basically toggles between 0 and 1, which makes sense. So I added an assignment to have the parity register power-up to 1 and reran the simulation.

Lo and behold, the counter began gray code counting backwards. Never knew they worked that way, but pretty interesting.

So... the parity bit is basically just inverting itself. If you had a glitch that caused it to have one extra toggle, then the parity bit will have an extra inversion, and the counter will count backwards.

(I think my case is the same thing, whereby the clock is glitching. If we move the clock to a PLL generated clock, it starts working.)

Anyway, I think you've already fixed it and knew the glitch was causing the problem, but it's nice to know what's going on at a more fundamental level. I'm just amazed this came up twice within 24 hours, and I'd never seen it for ten years prior.