Megawizard FIFO problem: Write and read request filling FIFO!

Thanks for your help. I have solved the problem.

Rysc,

The double negative was confusing "No overflow protection circuitry has been disabled." I meant the protection circuitry was enabled.

I was suggesting that the fact it remains broken for more than 64 cycles (the size of the fifo) it couldn't be a timing issue, as surely this would only result in a glitch of one or two cycles.

In the end it turned out the clock being fed into the FPGA (133Mhz) was terminated with an incorrect resistor value (22R). This resulted in the other FIFO clock (33Mhz), which was derived from the first being prone to glitches. I was able to trigger on this glitch on the scope, and it occurred at the same time the fifo started incrementing. What i can't understand is that the glitch only lasted for one clock cycle, yet the FIFO errors seem to last for multiple clock cycles (>10).

Thanks for all your suggestions.