Honored Contributor
Honored ContributorJust out of curiosity, your first post says the overflow circuitry is not enabled, but your second post says it is. Can you tap out the actual counters in the FIFOs(rather than used words, which is a calculated based on the counters). That was we can tell whether the counters are in the wrong spot or the calculations of usedwds is off. In fact, I would grab as many registers as you can out of the FIFO and compare good rdreqs to bad rdreqs. I would be extremely suprised if this is a device issue:
- If you do a different place and route, does the issue still occur? This will implement completely different logic, routing, etc., just the IO will be the same. - The fact that it works for a while and then goes off seems like a timing/functional issue. - Timing issues would not result in 64 clock cycles. I'm not sure why you're asking that? I'm assuming your logic has correctly raised the rdreq flag(for however many cycles), and it's just that the rdusedwds is incrementing that looks incorrect. Is there something else wrong?
