Megawizard FIFO problem: Write and read request filling FIFO!

Rysc/Gsynth,

The protection circuitry is still enabled, which should prevent any underrun/overflow situations and my PLLs are already both in use.

I'm starting to think its related to something else entirely, perhaps voltage or a manufacturing fault. I've checked the voltages and they seem normal.

If there is a timing problem and my constraints haven't detected it, could it really result in a request incrementing for more than 64 clock cycles? It just doesn't seem right.

Has anyone ever had a faulty FPGA? What were the indications?

Thanks for the suggestions.