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Honored Contributor
Honored ContributorMegawizard FIFO problem: Write and read request filling FIFO!
Hi, Well this has to be the most bizarre problem I've ever encountered. I've found that the read request signal to the fifo occasionally results in the fifo used counter to be incremented and t...
Altera_ForumHonored Contributor
Honored ContributorRysc/Gsynth,
The protection circuitry is still enabled, which should prevent any underrun/overflow situations and my PLLs are already both in use. I'm starting to think its related to something else entirely, perhaps voltage or a manufacturing fault. I've checked the voltages and they seem normal. If there is a timing problem and my constraints haven't detected it, could it really result in a request incrementing for more than 64 clock cycles? It just doesn't seem right. Has anyone ever had a faulty FPGA? What were the indications? Thanks for the suggestions.
