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Honored Contributor
Honored ContributorMegawizard FIFO problem: Write and read request filling FIFO!
Hi, Well this has to be the most bizarre problem I've ever encountered. I've found that the read request signal to the fifo occasionally results in the fifo used counter to be incremented and t...
Altera_ForumHonored Contributor
Honored ContributorBizarre indeed. Note that your read/write counters always increment, and the used words is just the difference between the two. Is it possible that, without protection circuitry, you've read past empty or written past full? This basically gets your counters to flip around each other, and so a read no longer moves the read counter toward your write counter(making the difference, rdusedwds get smaller), but it would be moving the read counter further away, making it get larger?
Can you make the two clocks outputs of a PLL? If so, they will be edge-aligned every third clock, and you no longer have to treat them as having asynchronous phases.
