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The rd_en and rd_clk come from the external microcontroller , the tri-state are there because in the full design the microcontroller would read and write to different FIFOs , but when i noticed this problem , i simplified the design just to help solve it . The design meets the timing constraints . U see the value that I write to the FIFO is (out_D<="0000111111111111"; )
or 0x0FFF in hex , the design is working fine with this value , but the problem is that if u just only change this value to 0xFFFF the operation screws !!!!!! , and again just changing this value to say 0x00FF the design works well again !!!!!!
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A possible scenario is that MSBs are corrupt across io. I don't know how you are observing result or what you mean by screw-up but one test is to pass MSBs as ones and LSBs as zeros e.g. 0xF000
As stated dc fifo cannot go wrong if interfaced correctly.
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