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Altera_Forum
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9 years ago

Measuring clock from DE0-Nano on scope

Hi, I have a clock divider in my design, that takes the 50MHz clock in the DE0-Nano board and divides it so that I get 1MHz in it's output (I can't use a PLL since 50M to 1M is impossible). ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks for the reply and sorry for my late one.

Like I said, a few weeks ago it worked. A few hours after writing this post, it started working again, so I forgot about this thread.

To answer your questions:

1. According to the Quartus pin planner, it is LV-TTL 3.3V

2. Yes, a reset signal zeroes the clock signal. It is the only signal that has any effect.

3. Now, Yes. Before I did not. I should mention I do not see a clear square wave but I assume that's because 50MHz is too high for the scope.

4. It is working.

One important thing I should mention - the clock signal from my clock divider I'm seeing now has a low maximum voltage. The DE2 pins, as far as I know, should have an output of 5V (like the VCC) or at least 3.3V. Problem is that the clock signal has a maximum voltage of 1.5V barely. Any known issue that can cause this?

Also, the same clock signal that is the output of the divider is used to clock many modules. I heard that in the assignment editor you can tell the Quartus program that this is the case by assigning it as a global clock or something like that. Is it true, and if it is, what is the correct assignment?

Thanks!