meaning of a pacKage

Package is a support vhdl program that is not meant to be a module like other design module but to insert any constants, functions in a neat way. It is optional. Most people use one package per project to insert their constants and functions. Others go as far as one package per module...too excessive.

type my_states is (s0, s1,s2....etc);

signal state : my_states;

means you create your own type, meaning a replacement for vhdl own types like std_logic etc. in order to help readability. For example it is convenient to use s0,s1,s2 than explicit binary value. The compiler then is free to encode the states.