Me and my simple questions: Can I do this in FPGA?

# ** Error: C:/Users/..../Downloads/altera/fixed_pkg_c.vhdl(22): Library ieee_proposed not found.# ** Error: C:/Users/..../Downloads/altera/fixed_pkg_c.vhdl(23): (vcom-1136) Unknown identifier "IEEE_PROPOSED".# # ** Error: C:/Users/..../Downloads/altera/fixed_pkg_c.vhdl(25): VHDL Compiler exiting

Model Sim doesn't like the VHDL 2008? Quartus II seems to compile, but when I try to use modelsim for simulating it gives me this error.

Tricky I've seen some of your answers regarding this question in the web.

I have done a file for adding binary unsigned fixed point numbers, and also a testbench loading two numbers to be added. Would you please say how to see the results of this addition ?