Forum Discussion
Wincent_Altera
Regular Contributor
11 months agoHi ,
Please accept my late response.
So agilex 5 FPGA Do actually have MIPI Standard IO (HS/LP Compatable IO), is the answer Correct !?.....
>> following user guide under https://cdrdv2-public.intel.com/834802/ug-817561-834802.pdf
>> There is a block who handles the external incoming data deserialization with its clocking for both HS and LP modes
Regards,
Wincent