MAXV - User Flash Memory Time Constraints

Hello,

I have still not been able to meet timing requirements with ALTUFM_SPI Block. I have defined an sdc file with four inputs and one output:

Inputs name: SCK - NCS - OSCENA - SI

Output name: SO

For some reason, I still get unconstrained paths even if it seems that all are constrained.

I still get warning messages and error messages like the one below:

------------

Warning (332009): The launch and latch times for the relationship between source clock: osc1 and destination clock: osc5 are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.

------------

Critical Warning (332148): Timing requirements not met

Someone would have some input regarding this?

Thanks,

Fabe

My SDC file is like below:

# SDC file

create_clock -name "osc1" -period 1000.0ns [get_ports {SCK}]

create_clock -name "osc2" -period 1000.0ns [get_ports {NCS}]

create_clock -name "osc3" -period 1000.0ns [get_registers {altufm_spi:inst|altufm_spi_m8s:auto_generated|dffe28}]

create_clock -name "osc4" -period 1000.0ns [get_registers {altufm_spi:inst|altufm_spi_m8s:auto_generated|dffe31}]

create_clock -name "osc5" -period 181.818ns [get_pins {inst|auto_generated|maxii_ufm_block1|osc}]

# Automatically constrain PLL and other generated clocks

derive_pll_clocks -create_base_clocks

# ###############################################################################################

# Block CPLD_EEPROM

# tsu/th constraints

# tco constraints

# tpd constraints

set_min_delay 10 -to [get_ports {SI}]

set_max_delay 80 -to [get_ports {SI}]

# set_min_delay 1 -to [get_ports {SCK}]

# set_max_delay 8 -to [get_ports {SCK}]

# set_min_delay 1 -to [get_ports {NCS}]

# set_max_delay 8 -to [get_ports {NCS}]

set_min_delay 10 -to [get_ports {OSCENA}]

set_max_delay 80 -to [get_ports {OSCENA}]

set_min_delay 10 -to [get_ports {SO}]

set_max_delay 80 -to [get_ports {SO}]