MAX10/DE10-Lite clock skew issue

Your code:

always @(Updown, Reset_n, Count)
  begin
    if (Reset_n == 0)
      next_Count <= 0;
    else if (Updown)
      next_Count <= Count + 1; // if Updown, increment Count
    else
      next_Count <= Count - 1; // else decrement Count
  end
always @(posedge Clock) // flip-flops
  Count <= next_Count; // count on rising clock edge

The problem is your fundamental design:

* The first always block is completely unclocked asynchronous logic.

* The second always block you have a one-rank synchronizer that synchronizes a multibit value (next_Count) to the clock.

The first always block will end up generating a large blob of combinatorial logic involving the Reset_N, Count[], and UpDown signals. Both UpDown and Reset_N are not clock synchronous.

Moving the design to be a fully synchronous counter, and adding input synchronization to the button push signal, should be much more tolerant of placement/routing timing variations:

Revised code:

reg UpDownSync1, UpDownSync2;
always @(posedge Clock)
  begin
    UpDownSync1 <= UpDown;
    UpDownSync2 <= UpDownSync1;
  end
always @(posedge Clock or negedge Reset_n)
  begin
    if (Reset_n == 0)
      Count <= 0;
    else if (UpDownSync2)
      Count <= Count + 1; // if Updown, increment Count
    else
      Count <= Count - 1; // else decrement Count
  end