SZand
New Contributor
New ContributorMAX10 using external PLL with soft-lvds gives always a warning: Warning (15064): PLL... jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
the LVDS signals are connected to a tft display. The picture is ok so far only, but after each comilation and program the fpga with more or less jitter. Compilation give the warning: Warning (15064...
Hi @SZand
Let me sum it up. There are 2 issues
1) warning on non-dedicated output clock
2) sdc constraint output paths
For (2), you might want to put on a new thread and refer to this thread so that my colleague could take detail look into your case.
For (1), Pll-c3(1:1): LVDS-clockpins which was supposedly your tx_outclock, should be connected to dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Example pin 32/33.
50/52 is not a dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Thus the warning.
There isnt any sdc constraint that can dismiss the warning.
