Forum Discussion
New ContributorMAX10 using external PLL with soft-lvds gives always a warning: Warning (15064): PLL... jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Hi @SZand
Let me sum it up. There are 2 issues
1) warning on non-dedicated output clock
2) sdc constraint output paths
For (2), you might want to put on a new thread and refer to this thread so that my colleague could take detail look into your case.
For (1), Pll-c3(1:1): LVDS-clockpins which was supposedly your tx_outclock, should be connected to dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Example pin 32/33.
50/52 is not a dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Thus the warning.
There isnt any sdc constraint that can dismiss the warning.
Frequent ContributorHi @SZand
I created a simple design with a MAX10 device. Inside this simple design there are:
1) SERDES block with Internal PLL
2) SERDES block with external PLL
I dont see the warning in either one.
I attached the QAR.
Meanwhile could you check if your clock out pin is connected to a dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp)?
if you are still facing problem, could you send me a simple design that shows the warning?
