MAX10 User-Specified ADC Logic Simulation Output

According the MAX 10 Analog to Digital Converter User guide:

"You can

configure the Altera Modular ADC or Altera Modular Dual ADC IP core to output user-specified

values in the logic simulation for each ADC channel except the TSD channel.If you enable this feature, you must provide a simulation stimulus input

file for each ADC channel thatyou enable. The logic simulation reads the input file for each channel and outputs the value of the currentsequence. Once the simulation reaches the end of the file, it repeats from the beginning of the sequence.

The

stimulus input file is a plain text file that contains two columns of numbers:• The first column of numbers is ignored by the simulation model. You can use any values that you wantsuch as time or sequence. The actual data sequencing is based on the text rows.

• The second column contains the voltage values."

Where can I enable this feature? I can not find this in the Qsys GUI. Does anybody know where to enable?