Thanks for the reply. My code is attached. Actually I tried simulating the design first but Modelsim gives these errors:
- Instantiation of 'altera_onchip_flash_avmm_data_controller' failed. The design unit was not found.
- Instantiation of 'fiftyfivenm_unvm' failed. The design unit was not found.
which I am unable to resolve, so moved directly to post synthesis verification.
Another thing that I have observed is if I remove the wait condition for 'readdatavalid' signal, it gets asserted by the UFM core and data is shared on the data bus but is mismatched from the address.
Besides can you explain, that you sent a read request for data to be read from 17'h00000 and 17'h00001 but it seems that UFM read some different data.
Regards
Sarmad