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KS_AX's avatar
KS_AX
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5 years ago

Max10 sometimes randomly stops operation, depending on settings in Signal Tap Logic Analyzer

Hello everyone, I ran into some unexpected behavior regarding the operation of my design on the MAX10 FPGA 10M08SAM153I7G. Now, first I have to say that I am quite new to Quartus/FPGA/Verilog and I...
IDeyn's avatar
IDeyn
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5 years ago

Hi KS_AX!

Well, if I understand correctly, your design takes a data from external port (bitstream).

Is it so?

If it is, when the issue is because you use comparison on bitstream value right inside your FSM.

It could be then a metastability issue. Try to synchronize bs port using two registers.

Metastability is the main reason I suppose why FSM can stop.

Hope it helps.

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Best regards,

Ivan