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SZand's avatar
SZand
Icon for New Contributor rankNew Contributor
7 years ago

MAX10 Soft-LVDS creates TimeQuest warnings

I am using the Soft-LVDS on 10M16SAE144 with external PLL, the LVDS pins are located in Bank3 (pins with full LVDS support) TimeQuest show some warnings regarding not fully constrained output paths ...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hi , When you select the Altera LVDS serdes IP you have use the timing constraints . The timing constraints can be done using timing analyzer tool or SDC FILE. Regards, RS