Occasional Contributor
Occasional ContributorI do not see any register or setting that disables the watchdog timer. Table 34 on page 62 gives no option to disable the watchdog timer and those are the only signals I have access to.
I connected the Dual Boot IP core using platform designer and saw a sample of the read and write waveforms and I recreated exactly the timing for reads and writes but I still cannot read anything. Trying to match the example waveforms makes it worse. See attached pictures for the example, my writes and my reads
Occasional ContributorAnother update, I now
1. write 1 to bit 0 of offset 2 and wait for this to happen (I think, there is no confirmation)
2. Read bit 0 of offset 3 and wait until this reads 0 (happens after ~150 clock cycles)
3. Read from offset 4. This now reads 0h0001FFFF. This is definitely better because I am pretty sure I am actually reading something, but bits [16:13] of this register are 1111 which does not correspond to an msm_cs value.
I am suspicious of the initial write since a previous forum post (https://community.intel.com/t5/Intel-FPGA-University-Program/MAX-10-FPGA-Remote-System-Upgrade-RSU/td-p/655190?profile.language=en) had this problem and it was fixed by writing to offset 2. I have tried waiting for over 531 clock cycles for this write to take place and have tried moving on right away like the avalon timing diagram mentioned above. Am I doing the writes wrong? Can this IP core even be simulated?
