I now found the solution for this problem. There are some level shifter connected to the FPGA. The output of these level shifters is 3,3V and during configuration all I/O pins of the FPGA are connected to GND. All in all the needed current consumption during configuration was to high (> 1A) and got limited by the power supply. So in the end the configuration failed.
I am now confused about the low state of the I/O pins during configuration. According to the "MAX10 configuration guide" these pins should be tri-state during configuration (see https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf, page 28, figure 10).
Is it possible to configure the state of the I/O pins during configuration?
Regards
Dennis