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Altera_Forum
Honored Contributor
8 years agoMAX10 PLL Not Locking - KHz instead of MHz
Greetings, We're using the 10M16DAF256I7G FPGA from the Max10 family. We're designing the firmware in VHDL and using Quartus to connect the blocks via schematics. 99% of our firmware is worki...
Altera_Forum
Honored Contributor
8 years agoTry connecting the input clock directly to the PLL's (adc_pll) inclock port , plus I don't see the reset as input to the PLL block. If you're not using the 'areset' pin, then enable the following option
- Enable self-reset on loss lock This will reset the PLL internally when it looses a lock and thus force it to regain lock again. Although I'd suggest you use the 'areset' pin and drive it from the system reset or POR from your board. The PLL may not be acquiring proper lock when its internal registers/FFs are not reset properly to a known state. The internal blocks in the PLL (PFD, NCO/VCO, etc) may need to be reset at the start, for it to capture and follow the incoming clock and get a lock on it.