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Honored Contributor
Honored ContributorMAX10 PLL Not Locking - KHz instead of MHz
Greetings, We're using the 10M16DAF256I7G FPGA from the Max10 family. We're designing the firmware in VHDL and using Quartus to connect the blocks via schematics. 99% of our firmware is worki...
Altera_ForumHonored Contributor
Honored ContributorHi,
I would recommend to go through below PLL loose lock debug checklist https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/support/devices/pll/pll-loss-of-lock-checklist.pdf Thanks. Regards, spdl2001 (This message was posted on behalf of Intel Corporation)
