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Honored Contributor
Honored ContributorMAX10 PLL External Clock Output
Hello there, I'm using the 10M08SCE144A7G FPGA. In my design I need to give a clk input signal to 3 diferents Analog to Digital Converters. I'm thinking of using a PLL External Clock Output (...
Altera_ForumHonored Contributor
Honored ContributorIs it a high frequency clock? If it's not too high it shouldn't be a problem to output the clock on a regular I/O instead of a dedicated PLL output. It is just a bit slower.
If you have problems meeting timing constraints with that solution, you can also use a DDS output, clocked with the PLL clock you want to export, and with the two SDR inputs set to 0 and 1. It will generate a signal with the same frequency, and usually a shorter delay than when connecting the clock directly to the I/O pin. If possible I'd recommend that you build a (at least) minimal Quartus project with your timing requirements and verify that you can meet them before committing the pins assignments on the PCB layout.
