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Altera_Forum
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8 years ago

MAX10 PLL External Clock Output

Hello there, I'm using the 10M08SCE144A7G FPGA. In my design I need to give a clk input signal to 3 diferents Analog to Digital Converters. I'm thinking of using a PLL External Clock Output (...
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Altera_Forum
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8 years ago

Hi JDL,

The MAX 10 PLLs can drive out to any regular I/O pin through the GCLK. You can refer to the MAX10 PLL user guide:

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_clkpll.pdf

Each PLL generates five clock outputs through the c[4..0] counters. Even though only the C0 output counter can feed to the dedicated external clock outputs without going through the GCLK, other output counters can feed other I/O pins through the GCLK. So you should be able to feed the PLL output to I/O pins.

Regards,

nyusof

(This message was posted on behalf of Intel Corporation)