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avib's avatar
avib
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

MAX10 I/Os state after JTAG operation

Hi, Can anyone tell what happens to the MAX10 after JTAG operation? Its I/Os float, its flip flops being cleared, it gets DEV_CLR, etc We have two MAX10 devices on our board connected together on...
AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hello Avi,

All configuration pins and JTAG pins in Intel MAX 10 devices are dual-purpose pins. The configuration pins function as configuration pins prior to user mode. When the device is in user mode, they function as user I/O pins or remain as configuration pins.

You can refer to Intel® MAX® 10 FPGA Configuration
User Guide for more details: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf

Thank you.

avib's avatar
avib
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thank you AminT

None of the dual purpose pins is connected to a signal that can cause the board reset. so I don't understand why it happens.

Thank you

Avi

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hello,

    The I/O state of the pin depends on what is set by the user on Quartus. Unused pin will be in week pull (set using unused pin settings) which means HIGH state or 1. You might get this problem from the transition from configuration mode to user mode. The I/O is expected to be in HIGH mode during the configuration and the state after that will depends on what is set by the user. You might also want to check if you have reset it as reset in user mode.

    Thank you.

    • avib's avatar
      avib
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi,

      When we enabled the Real Time ISP in the Quartus programmer the board didn't reset.

      Thanks you for your help

      Avi